One example of a programmable logic device is a system called a “field programmable gate array” (FPGA). An FPGA includes a plurality of logic blocks that are configurable, i.e., the user can program (i.e., write) a desired logic function.
In PCT publication WO2005/022380 filed by the present applicant, dynamic optimization of a hardware space composed of reconfigurable logic circuits is disclosed. This publication states that in a reconfigurable system, it is possible to greatly reduce the assigning of hardware resources to functions that are not being used or are in a standby state so that the hardware resources can be collectively assigned to the processing to which the hardware resources should be assigned. If a hardware space is optimized, it becomes no longer necessary to install all of the hardware circuits as in a conventional dedicated or special-purpose LSI. This means that high execution efficiency can be achieved with few hardware resources.
One well-known method for improving the processing performance of a general-purpose processor is to raise the clock frequency. However, raising the clock frequency of the entire system to improve system performance is often undesirable for reasons such as power consumption. It would be conceivable to raise the clock frequency of only a unit (or group of functional hardware resources) where the processing power is insufficient, in such case, it would be necessary to install a circuit or function that compensates for the difference in clock frequency between the unit(s) with the raised clock frequency and other units, such as an input/output circuit. Demands for improvements in processing performance are also limitless. When the performance of a system that already has a high clock frequency to carry out processing at high speed is no longer sufficient, it will become necessary to operate the system at an even higher clock frequency. As a result, it becomes necessary to solve the problems of large power consumption and large generation of heat.